1. Field of the Invention
The present invention relates in general to a complementary MOS semiconductor device which is suitable for a mobile apparatus, and more particularly to a complementary MOS semiconductor device in which even if gate insulating films of field effect transistors constituting a complementary MOS logic circuit are made less than 2.5 nm in thickness, the power consumption in non-operation is efficiently reduced.
2. Description of the Prior Art
In recent years, the demand for mobile apparatuses has increased. The mobile apparatuses presuppose the outdoor use of personal computers, portable telephones and the like, and the electric power is supplied to the mobile apparatuses by a battery. For this reason, in the mobile apparatuses, it is very important to reduce the power consumption in the non-operation thereof as well as the power consumption in the operation thereof. In addition, as for a semiconductor device for use in the mobile apparatus, in particular, a complementary MOS semiconductor device is effective because the complementary MOS semiconductor device has the lower power consumption in the non-operation thereof.
However, if a threshold voltage of a MOS FET is lowered in order to increase the circuit operating speed of a semiconductor device, the power consumption in non-operation becomes high since a current which is caused to flow in non-operation (hereinafter, referred to as "a stand-by current" for short, when applicable) is increased. FIG. 4 is a circuit diagram showing a configuration of a circuit which is incorporated in a conventional complementary MOS semiconductor device. The conventional complementary MOS semiconductor device has two-stages inverters INV11 and INV12 incorporated therein. The inverter INV11 includes a p-channel MOS FET P11 and an n-channel MOS FET N11, and the inverter INV12 includes a p-channel MOS FET P12 and an n-channel MOS FET N12. Each of these MOS FETs P11, P12, N11 and N12, is a low threshold voltage MOS FET having a low threshold.
In the conventional complementary MOS semiconductor device thus configured, when a signal input to an input terminal IN11 which is connected to both of a gate of the p-channel MOS FET P11 and a gate of the n-channel MOS FET N11 which are provided in the inverter INV11 is held at a low level, the p-channel MOS FET P11 is in a conduction state, while the n-channel MOS FET N11 is in a nonconducting state. In this case, a signal input to the inverter INV12 is held at a high level so that the p-channel MOS FET P12 becomes a nonconducting state, while the n-channel MOS FET N12 becomes a conduction state. Then, a signal at a low level is output through an output terminal OUT11 which is connected to both of a drain of the p-channel MOS FET P12 and a drain of the n-channel MOS FET N12. At this time, though in the inverter INV11, the n-channel MOS FET N11 is in a nonconducting state, in actual, a large stand-by current is caused to flow resulting from that the MOS FET is of the low threshold voltage type. For this reason, a through current 21 corresponding to this stand-by current is caused to flow through the path extending from a power source line L11 to a GND line L12. In addition, in the inverter INV12, a through current 22 corresponding to a stand-by current of the p-channel MOS FET P12 is caused to flow through the path extending from the power source line L11 to the GND line L12. These through currents 21 and 22 result in the power consumption in non-operation being increased.
Then, the circuit which is designed in order to solve the above-mentioned disadvantage is proposed (refer to Japanese Patent Application Laid-open No. Hei6-29834). The circuit disclosed in this official gazette is designed on the basis of the logic circuit shown in FIG. 4, and there is provided therein means for separating the power source line and the GND line from that logic circuit. FIG. 5 is a circuit diagram showing a configuration of the circuit disclosed in Japanese Patent Application Laid-open No.Hei6-29834. In this connection, in the circuit shown in FIG. 5, parts similar to those in the logic circuit shown in FIG. 4 are denoted by the same reference numerals, and the detailed description thereof is omitted here for the sake of simplicity. In the circuit disclosed in Japanese Patent Application Laid-Open No. Hei 6-29834, a p-channel MOS FET P13 is provided as a power supply circuit S11 across a power source line L13 and a pseudo power source line V11, and also an n-channel MOS FET N13 is provided as a power supply circuit S12 across a GND line L14 and a pseudo GND line V12. Each of the p-channel MOS FET P13 and the n-channel MOS FET N13 is a high threshold voltage MOS FET having a high threshold. Now, a gate of the p-channel MOS FET P13 is connected to a switch SW11 through an inverter INV13, while a gate of the n-channel MOS FET N13 is connected directly to the switch SW11.
In the conventional circuit configured as described above, if the switch SW11 is caused to be a nonconducting state in non-operation by the inverters INV11 and INV12, both of the p-channel MOS FET P13 and the n-channel MOS FET N13 become a nonconducting state so that both of the inverters INV11 and INV12 are separated from the power source line 13 and the GND line 14. In addition, since each of the p-channel MOS FET P13 and the n-channel MOS FET N13 is the high threshold voltage MOS FET, the stand-by current thereof is remarkably thinner than that of the MOS FETS P11, P12, N11 and N12, and hence the through current which is caused to flow through the path extending from the power source line L13 to the GND line L14 is remarkably suppressed. As a result, the power consumption in non-operation is remarkably reduced.
In addition, there is proposed a circuit which is capable of reducing the power consumption in non-operation without reducing the operating speed (refer to Japanese Patent Application Laid-open No. Hei 7-38417). In the circuit disclosed in this official gazette, a first inverter comprised of a MOS transistor having a low threshold voltage and a second inverter comprised of a MOS transistor having a high threshold voltage are provided in a logic circuit. Further, the first inverter is designed in such a way as to be separated from a power source in the non-operation thereof.
According to the circuit disclosed in Japanese Patent Application Laid-open No. Hei 7-38417, during the operation, the high speed switching operation is carried out by the first inverter, while during the non-operation, the output level is held by the second inverter. For this reason, the power consumption in the non-operation can be suppressed to the remarkably low value.
However, there arises the problem that when MOS FETs are shrunk finely along with the promotion of the high speed operation and the high integration of LSIs so that the gate length becomes about 0.1 .mu.m, in the conventional complementary MOS semiconductor device in which the circuit configured as described above is incorporated, the power consumption thereof in the non-operation is high. In particular, since in an LSI which is operated by a battery, even in the non-operation as well, the remarkably high power consumption is generated and the battery consumption becomes remarkable. In the present circumstances in which the demand for the mobile apparatus is more and more increased, it is very important to solve this problem.
The device parameters such as size and the like of MOS FETs are finely shrunk in accordance with a certain proportional scale down rule. As for the proportional scale down rules, there have been proposed the electric field--definite proportional scale down rule, the voltage--definite proportional scale down rule, the quasi-electric field--definite proportional scale down rule and the like. Then, in any of the proportional scale down rules, it is presupposed to shrink both of the gate length and the thickness of the gate insulating film with the same scale down ratio. In the actual devices as well, the gate length and the thickness of the gate insulating film are approximately, proportionally shrunk. Therefore, since the thickness of the gate insulating film of a CMOS with 0.25 .mu.m gate length is in general 5 nm, it is introduced from the proportional scale down rule that the thickness of the gate insulating film of a CMOS with about 0.1 .mu.m gate length is in the range of 2.0 to 2.5 nm. That is, if in order that a MOS FET may be finely shrunk, the gate length is made about 0.1 .mu.m and the thickness of the gate insulating film within a logic circuit is made thinner than 2.5 nm, then the power consumption in non-operation will be increased.